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e9fb3b3fc0
* Sycl tp stage1 (#1) * SYCL: tensor parallelism (--split-mode tensor) for dual-GPU Adds the comm_init/comm_free/comm_allreduce_tensor trio that the meta-backend queries via get_proc_address to enable backend-specific all-reduce, mirroring the pattern used by ggml-cuda.cu. For N=2 (the common dual-GPU case) implements a degenerate ring all-reduce with two size-branched paths: * Small (nelem < 32768): FP32 direct memcpy + per-device ADD kernel chained via depends_on(memcpy_event). 4 SYCL submissions/call. * Large (nelem >= 32768): BF16-compressed. Each device compresses FP32 -> BF16 in a local outbox, cross-device memcpys to the peer's inbox (HALF the PCIe bytes), then decompresses + adds into the local FP32 partial. 6 SYCL submissions/call but PCIe bytes halved -- wins for any tensor where PCIe dominates kernel time. Threshold and BF16 path pattern mirror the CUDA NCCL allreduce. Storage: ONE persistent uint8_t buffer per device, 4 * nelem bytes (matches both path layouts: FP32 nelem floats; BF16 outbox+inbox = 2 * nelem uint16_t each). Single alloc+free per device keeps the SYCL pool's strict-LIFO invariant trivial. Initial impl handles N=2 FP32 contiguous tensors. Other cases return false, causing the meta-backend to use its generic butterfly fallback. Per-call sync is intentionally omitted. SYCL in-order queue semantics ensure that the meta-backend's next compute on the same per-device queue waits for our final ADD, and the next allreduce's first op on the same persistent buffer waits via the same queue. Only comm_free does an explicit final wait. OneCCL is NOT used: OneCCL 2021.17 hardcodes single-device-per-process in communicator_impl.hpp:47 (condition devices.size() == 1), which is incompatible with llama.cpp's single-process multi-GPU model. Measured on dual Intel Arc Pro B70 (NEO 26.05.x, oneAPI 2025.3 + DPC++ nightly): Llama-3.3-70B Q4_K_M, -sm tensor -fa 1 -ctk f16 -ctv f16: pp512 = 377.08 t/s (vs 313.65 layer mode = +20.2%) tg128 = 17.40 t/s (vs 9.74 layer mode = +78.6%) Qwen3-Coder-Next-80B-A3B Q3_K_M (MoE): pp512 = 216.56 t/s (vs 156.58 meta-backend butterfly = +38.3%) tg128 = 17.60 t/s (vs 14.31 meta-backend butterfly = +23.0%) Qwen3-4B Q4_K_M: pp64 = 984.51 t/s, tg16 = 49.29 t/s Llama-3.3-70B in SYCL TP now comfortably beats production layer mode on both prefill and decode. Coder-Next-80B-A3B (MoE) also wins on both — the BF16 path is what unlocks the many-medium-allreduces prefill pattern. Build/CMake: no changes. No new dependencies. ~210 lines added across ggml-sycl.h and ggml-sycl.cpp. * Fix comments * documentation update to address PR feedback * Bring over my device-to-device memcpy chagnes * move the dev2dev_memcpy calls to the upstream 7-parameter variety * Fix a typo and remove a trailing whitespace
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
//
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// MIT license
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// Copyright (C) 2024 Intel Corporation
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// SPDX-License-Identifier: MIT
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//
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#pragma once
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#include "ggml.h"
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#include "ggml-backend.h"
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#define GGML_SYCL_NAME "SYCL"
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#define GGML_SYCL_MAX_DEVICES 48
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#ifdef __cplusplus
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extern "C" {
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#endif
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// backend API
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GGML_BACKEND_API ggml_backend_t ggml_backend_sycl_init(int device);
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GGML_BACKEND_API bool ggml_backend_is_sycl(ggml_backend_t backend);
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// devide buffer
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GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_sycl_buffer_type(int device);
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// split tensor buffer that splits matrices by rows across multiple devices
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GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_sycl_split_buffer_type(const float * tensor_split);
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// Tensor parallelism (--split-mode tensor): comm_init/free/allreduce_tensor
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// trio queried by the meta-backend via ggml_backend_reg_get_proc_address.
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// See typedefs in ggml/include/ggml-backend.h. Mirrors the CUDA backend's
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// pattern (ggml_backend_cuda_comm_*).
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GGML_BACKEND_API void * ggml_backend_sycl_comm_init(ggml_backend_t * backends, size_t n_backends);
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GGML_BACKEND_API void ggml_backend_sycl_comm_free(void * comm_ctx);
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GGML_BACKEND_API bool ggml_backend_sycl_comm_allreduce_tensor(void * comm_ctx, struct ggml_tensor ** tensors);
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// pinned host buffer for use with the CPU backend for faster copies between CPU and GPU
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GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_sycl_host_buffer_type(void);
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GGML_BACKEND_API void ggml_backend_sycl_print_sycl_devices(void);
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GGML_BACKEND_API void ggml_backend_sycl_get_gpu_list(int *id_list, int max_len);
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GGML_BACKEND_API void ggml_backend_sycl_get_device_description(int device,
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char *description,
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size_t description_size);
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GGML_BACKEND_API int ggml_backend_sycl_get_device_count();
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GGML_BACKEND_API void ggml_backend_sycl_get_device_memory(int device, size_t *free, size_t *total);
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// SYCL doesn't support registering host memory, keep here for reference
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// GGML_BACKEND_API bool ggml_backend_sycl_register_host_buffer(void * buffer, size_t size);
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// GGML_BACKEND_API void ggml_backend_sycl_unregister_host_buffer(void * buffer);
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GGML_BACKEND_API ggml_backend_reg_t ggml_backend_sycl_reg(void);
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#ifdef __cplusplus
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}
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#endif
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